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概要
Experienced Executive Engineer with a demonstrated history of working in Embedded Systems Design. Skilled in FPGA based real-time Signal Processing, Telecommunication, and Computer Architecture. Strong engineering professional with a Master’s Degree focused on Electrical, Electronic, and Embedded Systems from Lahore University of Management Sciences.
项目
工作经历
FPGA Design Engineer
RTL Design and implementation of DSP algorithms for RF/digital wireless communications Systems using VHDL and Verilog HDL
Xilinx toolchain including Vivado 2019.1, SDK and HLS
Worked on High-End FPGAs like Zynq 7035, 7020, Virtex 7, and Zynq Ultra-Scale devices
Worked on PS-PL communication using AXI standards and IP driver development for the ARM A9 processor
Petalinux tools to customize the boot loaders, Linux kernel, embedded Linux file Systems based on customized PL designs in Xilinx FPGAs and SoCs
Worked closely with cross-functional teams, including Front-end, Quantitative Research, Engineering, and marketing teams
Worked on interfacing Texas Instruments (TI) based ADC and DAC with Xilinx Zedboard and ZC707
Designed and implemented waveforms and DSP algorithms like (frequency detection, local maxima and minima, clock domain crossing, DDS, FIR, CORDIC, FFT) using VHDL or Verilog targeting various Software Defined Radio (SDR) hardware like ad9361, ad9371, and ad9009
Proficient in the use of Lab Equipment like Oscilloscopes, Signal Generator, Spectrum Analyzer, Logic Analyzer, RF-Power sensor, Digital Multimeter.
Familiar with common data communication protocols like SPI, I2C, UART, USART, USB
Teacher's Assistant
I was also responsible to prepare and conduct the RTL design tutorial lab sessions on Xilinx Basys 2, Nexys 3, Nexys 4, and Zedboard FPGA development Kit using Verilog HDL.
